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Year of fee payment: Error detection mechanisms for devices that have multilevel signal interfaces test multilevel signals of an interface with a binary test apparatus. The error detection mechanisms include converting between multilevel signals of the interface and binary signals of the test apparatus.

The error detection mechanisms also include repeated transmission of multilevel signals stored in a memory of a device having a multilevel signal interface for detection by the test apparatus at different binary levels. The present invention relates to multilevel digital signaling, and in particular to techniques to test for errors that may occur in a multilevel, multi-line signaling system. The use of multiple signal levels instead of binary signal levels is a known technique for increasing the data rate of a digital signaling system, without necessarily increasing the signal frequency of the system.

Such multilevel signaling is sometimes known as multiple pulse amplitude modulation or multi-PAM, and has been implemented with radio or other long-distance wireless signaling systems. Multi-PAM has not traditionally been used for communication between devices in close proximity or belonging to the same system, such as those connected to the same integrated circuit IC or printed circuit board PCB.

One reason for this may be that within such a system the characteristics of transmission lines, such as buses or signal lines, over which signals travel are tightly controlled, so that increases in data rate may be achieved by simply increasing data frequency. At higher frequencies, however, receiving devices may have a reduced ability to distinguish binary signals, so that dividing signals into smaller levels for multi-PAM is problematic.

Multi-PAM may also be more difficult to implement in multi-drop bus systems i. Testing of a multi-PAM device is also problematic, since test apparatuses are typically designed for testing binary signals. Thus, in addition to the complexities of designing a multi-PAM device, there may not be conventional means for testing a multi-PAM device to ensure that the device operates free of errors.

The present invention is directed to error detection mechanisms for multilevel signal interfaces. Such error detection mechanisms may involve translating between the multilevel signals of an interface and binary signals of a test apparatus. The error detection mechanisms may be particularly advantageous for testing integrated circuits designed to communicate according to multi-PAM signals over printed circuit boards.

Although four logical states are illustrated in this example, a multilevel signal system may have more or less logical states, with at least two reference levels serving as boundaries between the states. A first bit of each logical state is termed the most significant bit MSB and a second bit of each logical state is termed the least significant bit LSB.

Each logical state may be termed a symbol, since it provides information regarding more than one bit. Data may be transmitted and read at both rising and falling edge of a clock cycle, so that each bit signal and each dual-bit signal has a duration of one-half the clock cycle. The logical states are arranged in a Gray coded order, so that an erroneous reading of an adjacent logic state produces an error in only one of the bits. Alternatively, the logical states can be arranged in numerical 00, 01, 10, 11 or other order.

In one embodiment the communication system is employed for a memory bus that may for instance include random access memory RAM , like that disclosed in U. An output driver 20 drives signals to output pad 18 and over transmission line 16 , which may for example be a memory bus or other interconnection between devices affixed to a circuit board, to be received at pad Transmission line 16 has a characteristic impedance Z 0 27 that is substantially matched with a terminating resistor 29 to minimize reflections.

Control signal input through lines C 1 , C 2 and C 3 switch respective current sources 21 , 22 and 23 on and off. The logical level 00 is chosen to have zero current flow to reduce power consumption for the situation in which much of the data transmitted has a MSB and LSB of zero. The use of differential signaling can provide increased immunity to noise and crosstalk. A voltage V 1 on one of the wires varies over time between four voltage levels, as shown with solid line 50 , while a voltage V 2 on the other wire also varies between the four voltage levels but in a complementary fashion, as shown with broken line Another example of a multilevel signaling apparatus and method is disclosed in U.

This and other types of multilevel signal interfaces may also be tested in accordance with the present invention. Also incorporated by reference herein is a U. Multiplexers , and select the odd or even signals according to a clock select signal on select line , outputting the thermometer code control signals on lines C 1 , C 2 and C 3.

Encoder is shown in more detail in FIG. As mentioned above, the data may be transmitted at twice the clock frequency, and a substantially identical receiver is shown in FIG. Although this embodiment discloses data sampling at both rising and falling clock edges, data may alternatively be sampled at only the rising clock edges or only the falling clock edges.

The latching comparators , and may be implemented as integrating receivers to reduce the sensitivity of the output signals to noise. This can be accomplished by integrating the difference between the received signal, Vin, and the three respective reference voltages over most or all of the bit cycle, and then latching the integrated results as the outputs A, B and C. Related disclosure of a multi-PAM signaling system can be found in U.

Memory may store binary or other forms of data using semiconductor, magnetic, optical, ferroelectric or other known means for storage. Data signals from memory are clocked with transmit clock signals and encoded at encoder , which provides control signals to output driver The output of receiver is clocked with receive clock signals and decoded into binary signals at decoder to be output as data Receiver and decoder may be similar to receiver described previously.

Test apparatus may be conventional, such as model number or High Speed Memory tester, available from Agilent Technologies, Palo Alto, Calif. Test interface may be a printed circuit board adapted to provide electrical and mechanical connections between test apparatus and DUT , and may be termed a load board. Examples such load boards are described in U. As mentioned above, DUT contains a multilevel signal interface and memory Communication of binary signals with a multilevel signal interface can be accomplished by use of appropriate control signals, for example by setting LSB equal to zero for all states input to the encoder and output driver 20 described previously.

In either case, the DUT may be tested for errors in binary signals as well as tested for errors in multilevel signals. This testing of binary and multilevel signals can be done during the same or different insertions of DUT into load board For the case in which the binary and multilevel signals are tested during the same insertion of DUT into load board , the binary testing can be performed at one time, and the multilevel testing performed at another time.

The eye diagram represents the ranges of transmissions voltages and signal transmission times for which data transmission is successful. The width of each eye represents the range of signal transition times, compared to an ideal center time, which still results in successful data transmission. The height of each eye represents the amount of voltage error and noise that a DUT can tolerate, as compared with an ideal central voltage level. Testing determines the range of transmission voltages and signal transition times for which the DUT can successfully receive data and compares this region to some voltage and timing criteria appropriate for the system.

Receiver testing may be done by repeatedly sending data to the DUT using different transmission voltages and signal transmission times and measuring the region for which transmission was successful. As shown in FIG. In an upper portion of FIG. In a lower portion of FIG. Each of the six 2-PAM sequences can be tested by varying each of the receive reference levels that a signal transition crosses, while holding the others constant.

Passes 1,4, and 6 need only be tested by varying one of the three references. In total, six 2-PAM sequences are tested a total of ten times. Table 2 lists MSB and LSB values for the passes, as well as the reference levels that are checked, with those that are not checked being marked with an X. Alternatively, a sequence of test signals generated by test apparatus may be stored in the memory of the DUT and then transmitted repeatedly from the DUT to the test apparatus, which is programmed to detect different levels of binary signals each time the sequence is received.

The test system includes a conventional test apparatus designed for testing devices employing binary signals, such as described above. The test apparatus may have one or more test drivers and that output binary signals based upon inputs from a signal controller Similarly, test apparatus may have one or more test receivers and that categorize signals received from a DUT as binary signals. For example, signal controller may be a program executed by the test apparatus , including a sequence of digital signals designed to test for errors in DUT A comparison mechanism of error detector , such as a plurality of comparitors or a plurality of XOR or XNOR gates, can then determine whether the binary sequence received by test receivers and matches the binary sequence earlier output by test drivers and Alternatively, error detector may be a part of a test program executing on apperatus Conversely, DUT may produce a PRBS signal and the test receivers and check the received sequence against a program provided to error detector In this manner the input receiver and output driver can be independently tested without using memory In a conventional implementation, in contrast to that shown in FIG.

In the embodiment shown in FIG. A multilevel input receiver of DUT decodes the multilevel signal and outputs a sequence of binary signals to memory DUT thus can store the multilevel signal received from test system , and then output that multilevel signal repeatedly for testing by at least one of the binary test receivers and , with the test receivers measuring a different binary threshold when the multilevel signal is repeated.

To do this, output driver encodes the sequence of binary signals output by memory and transmits the resulting multilevel signal to test interface , which is coupled to test receivers and Test receivers and can be set to different voltage levels, to decode the multilevel signal they received into binary MSB and LSB components that are validated by error detector An optional power combiner is provided on test interface that also serves as a matched attenuator to minimize reflections of the signals output by power combiner During a second sequence of signals from memory , test receiver can be set to have a binary threshold that matches VREFM, and during a sequence of signals from memory , test receiver can be set to have a binary threshold that matches VREFL.

The binary output of test receiver can then be compared by error detector with an expected pattern determined by the sequence of signals input into test drivers and Table 3 shows the logic levels at various locations in the system of FIG.

Control signals shown in a third column are input into test drivers and to create the four voltages, with the MSB voltage output from driver weighted twice that of the LSB voltage output from driver , as described above. Other coding schemes are possible; for example column 2 may be binary rather than Gray coded. Also, a system where signals swing symmetrically above or below a reference voltage may require different symbol mappings in columns 3 and 4.

Test receivers and can both receive signals from a single pin of the DUT and can be set to different binary thresholds, so that testing of DUT for errors in a sequence of combined signals transmitted by test drivers and can be accomplished in only two transmissions of that sequence from DUT to test receivers.

Connection of a third test receiver to the DUT pin, in addition to test receivers and , allows testing to proceed without repeatedly transmitting the sequence from memory. Certain test apparatuses e. Alternatively, two such dual-voltage digital receivers connected to a DUT pin can analyze 4-PAM signals without repeating those signals. Similarly matched is the impedance Z 1 of a portion of the test interface connecting receiver with DUT Table 4 shows the voltage levels at drivers and that provide the signal levels of Table 3 at the DUT pin.

Receiver , which is not shown in this figure, may also be able to detect plural voltage levels. For the situation in which the receiver of FIG. While the signal seen at receiver would be reduced for the matched attenuator embodiment compared to the power splitter embodiment, load board resistors may provide a better termination and therefore reduce reflections when test drivers and write to DUT Reducing reflections is important in a multilevel signaling system because reflected energy decreases voltage margins that have already been reduced by splitting the signal into multiple voltage levels.

Interface circuitry can also include circuits for converting binary signals from test apparatus drivers to multilevel signals that are input into a receiver at DUT Interface circuitry may be provided as an integrated circuit IC chip and may include circuits similar to those shown in FIG. Although we have focused on teaching the preferred embodiments of testing, with a binary test apparatus, a device including a multilevel signal interface, other embodiments and modifications of this invention will be apparent to persons of ordinary skill in the art in view of these teachings.

Therefore, this invention is limited only by the following claims, which include all such embodiments, modifications and equivalents when viewed in conjunction with the above specification and accompanying drawings.